Method and apparatus for control of another device through an ide bus

ABSTRACT

A method and apparatus for an IDE device to control a second device through an IDE bus. The IDE device includes firmware, a microprocessor, and a plurality of registers. The IDE device can read specific registers in the second device by storing a value indicating the request in a register of the IDE device and issuing an Interrupt signal (INTRQ). An implementation circuit in the second device then makes the contents of the specific register available to be read by the IDE device and clears the INTRQ. Similarly, the IDE device can write to a specific register of the second device by storing the request and the data to be written into predetermined registers in the IDE device and issuing an INTRQ signal. The implementation circuit then causes the data to be written into the specific register of the second device indicated by the request and clears the INTRQ.

BACKGROUND OF INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to control of another devicethrough an Integrated Drive Electronics (IDE) bus. More specifically, anapparatus and method for an IDE device to control another device throughthe bus, reducing the cost and complexity of a second devicecommunicating with the IDE device, is disclosed.

[0003] 2. Description of the Prior Art

[0004] The modularization of components for many of todays electronicdevices has benefited manufacturers and consumers alike. The consumerhas the flexibility to select from a variety of components or addadditional hardware according to his or her needs. The manufacturer hasthe advantages of specialization, reducing costs and increasingperformance of the particular component. One quite common example ofsuch an arrangement is the ability of the user to add a device, such asan optical disc drive, to a preexisting host computer system.

[0005] As with non-modularized systems, a basic requirement for theproper functionality of the system is establishing a protocol foreffective communications between the various components and the hostsystem. Therefore, a variety of industry standard communicationprotocols have been developed and are currently in use, such as versionsof a Universal Serial Bus (USB), Integrated Drive Electronics (IDE), andSmall Computer System Interface (SCSI) interfaces as a few examples. Aslong as the host system and the component utilize the same protocol,communications allowing the proper functioning of the component arepossible.

[0006] An obvious communication problem occurs when a user wishes toattach a device that uses one protocol to a system connection using adifferent protocol, for example connecting an external IDE device to aUSB port of the system. In this situation an intermediate device, orbridge, is often used between the device and the host system to permiteffective communications.

[0007]FIG. 1 is a functional block diagram of conventionalHost-Bridge-Device system 10. The system 10 comprises a host 15, abridge 20, and a device 25. A first bus interface 30 connects the host15 with the bridge 20 and allows communications between the host 15 andthe bridge 20 according to a first communications protocol. A second businterface 35 connects the bridge 20 with the device 25 and allowscommunications between the bridge 20 and the device 25 according to asecond communications protocol. The second communications protocol usedin the Host-Bridge-Device system 10 is a version of Integrated DeviceElectronics (IDE).

[0008] The bridge 20 comprises a circuitry 50 to control the operationsof bridge 20. The circuitry 50 comprises a microprocessor 60, a memory65, and a microprocessor interface 55. The bridge 20 further comprises aplurality of registers 75 used for controlling the functions of thebridge 20. The registers 75 may be comprised within the memory 65 orthey may be comprised elsewhere within the bridge 20 according to designconsiderations. The device comprises a microprocessor 90, firmware 95,and a corresponding plurality of registers 85 used for the transfer ofdata and control instructions to and from the bridge 20. The memory 65may be volatile and/or non-volatile and is used to store computer code70 that is executed by the microprocessor 60 to effect control of thebridge 20. The bridge 20 accesses the device 25 through the IDE bus 35by the reading and writing of data and control instructions to and fromthe registers 85 in the device 25. The microprocessor 60 controls thebridge 20 to access the device 25 by the reading and writing of data andcontrol instructions to and from the registers 75 in the bridge 20.

[0009] While the above-described circuitry 50 is capable of controllingthe operations of bridge 20, the inclusion of the circuitry 50 tocontrol the operations of bridge 20 raises the cost and complexity ofthe bridge 20.

SUMMARY OF INVENTION

[0010] It is therefore a primary objective of the claimed invention toreduce the cost and complexity of a Host-Bridge-Data Storage Devicesystem by using the data storage device to control the bridge, throughan Integrated Device Electronics (IDE) bus.

[0011] Briefly summarized, the preferred embodiment of the claimedinvention discloses an apparatus and method that allow the data storagedevice to control the other device, such as a bridge, through the IDEbus. Because an IDE data storage device already includes the circuitrynecessary for control of the other device, the necessary circuitry canbe eliminated from the other device. Only a change to the firmwarealready included in the IDE data storage device is necessary tosuccessfully implement control of the other device through the IDE bus.

[0012] The claimed invention includes an IDE data storage device thatcan control another device through an IDE bus. A first end of the IDEbus can be connected to the IDE data storage device and a second end ofthe IDE bus can be connected to a second device, such as a bridge, hostcomputer, or other apparatus, the IDE bus allowing the IDE data storagedevice and the second device to communicate according to the IDEprotocol. The IDE data storage device includes firmware includingcomputer code for implementing control of the second device, amicroprocessor for executing the computer code, and a plurality ofregisters for the transfer of data and control instructions. The seconddevice comprises a plurality of registers and an implementation circuitfor carrying out requests received from the IDE data storage device. Theimplementation circuit preferably is hardwired but may be put intopractice using other methods known in the art, such as via firmware orsoftware.

[0013] According to the present invention, the IDE data storage devicecan read specific registers in the second device by storing a value therequest in a predetermined register or registers of the IDE data storagedevice and issuing an Interrupt signal (INTRQ). The implementationcircuit of the second device then makes the contents of the specificregister available to be read by the IDE data storage device and clearsthe INTRQ. Similarly, the IDE data storage device can write to aspecific register of the second device by storing the request and thedata to be written into a predetermined register or registers in the IDEdata storage device and issuing an INTRQ signal. Upon receiving theINTRQ signal, the implementation circuit of the second device thencauses the data to be written into the specific register of the seconddevice indicated by the request and clears the INTRQ.

[0014] It is an advantage of the claimed invention that the IDE datastorage device can control the second device through an IDE bus,reducing the cost and complexity of the second device when communicatingwith the IDE data storage device using an IDE communications protocol.

[0015] These and other objectives of the claimed invention will no doubtbecome obvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment, which isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0016]FIG. 1 is a functional block diagram of conventionalHost-Bridge-Device system.

[0017]FIG. 2 is a functional block diagram of Host-Bridge-Device systemaccording to the present invention.

[0018]FIG. 3 is a flowchart of the device according to the presentinvention reading a bridge register.

[0019]FIG. 4 is a flowchart of the device according to the presentinvention writing to a bridge register.

DETAILED DESCRIPTION

[0020] In this application, the term Integrated Device Electronics (IDE)is defined to encompass all protocols based upon IDE technology,including Advanced Technology Attachment (ATA), Advanced TechnologyAttachment Packet Interface (ATAPI), and Serial ATA. In addition, inthis application, the term IDE data storage device, such as variousforms of data storage devices including a hard disk drive and an opticaldisc drive, refers to an apparatus requiring an IDE communicationsconnection with a second device for proper functionality.

[0021]FIG. 2 is a functional block diagram of a Host-Bridge-Devicesystem 100 according to the present invention. Where the components andfunctionality of the components are the same as depicted in FIG. 1, theoriginal reference numbers have been maintained for clarity.

[0022] The system 100 comprises a host computer system 15, a bridge 120,and a data storage device 125. A first bus interface 30 connects thehost 15 with the bridge 120 and allows communications between the host15 and the bridge 120 according to a first communications protocol. Asecond bus interface 35 connects the bridge 120 with the data storagedevice 125 and allows communications between the bridge 120 and the datastorage device 125 according to a version of Integrated DeviceElectronics (IDE) communications protocol.

[0023] The data storage device 125 comprises a microprocessor 90,firmware 195 comprising computer code for operating the data storagedevice 125 and for controlling the bridge 120, and a plurality ofregisters 85 used for the transfer of data and control instructions toand from the bridge 120. The bridge 120 of the present invention doesnot comprise the prior art control circuitry 50 depicted in FIG. 1.However, the bridge 120 does comprise a corresponding plurality ofregisters 75 for realizing the bridge functions. The bridge 120 furthercomprises an implementation circuit 80 for carrying out requestsreceived from the data storage device 125. The implementation circuit 80is hardwired in a preferred embodiment of the present invention butanother embodiment may employ an implementation circuit that is nothardwired, such as being software instructions coded in firmware oranother form of memory.

[0024] As is known in the art, control of the bridge 120 is affected bythe reading and writing to and from the registers 75. The presentinvention utilizes the IDE bus 35 and a firmware-only modified IDE datastorage device 25 instead of all those elements inside the dash-linedblock 50 in FIG. 1. Please refer to FIG. 3 and FIG. 4 which areflowcharts demonstrating how this is done according to the presentinvention.

[0025]FIG. 3 illustrates the present invention method of how the IDEdata storage device 125 can read one of the registers 75 in the bridge120. The steps shown in FIG. 3 include the following:

[0026] Step 400: The IDE data storage device 125 stores a firstinstruction into a first predetermined register 85 in the IDE device125, the value of the first instruction indicating a read request andwhich register 75 in the bridge 120 is to be read.

[0027] Step 410: The IDE data storage device 125 sets an InterruptRequest (INTRQ) signal high.

[0028] Step 420: The bridge 120 receives the INTRQ from the IDE datastorage device 125 and checks the contents of the first predeterminedregister 85.

[0029] Step 430: The implementation circuit 80 receives the contents ofthe first predetermined register 85 and causes the contents of theindicated register 75 to be placed into a second predetermined register85 in the IDE data storage device 125.

[0030] Step 440: The bridge 120 clears the INTRQ.

[0031] Step 450: The IDE data storage device 125 reads the secondpredetermined register 85 in the IDE data storage device 125.

[0032]FIG. 4 illustrates the present invention method of how the IDEdata storage device 125 can write to one of the registers 75 in thebridge 120. The steps shown in FIG. 4 include the following. Obviously,the order of steps 500 and 510 can be reversed.

[0033] Step 500: The IDE data storage device 125 stores a secondinstruction into a third predetermined register 85 in the IDE datastorage device 125, the value of the second instruction indicating awrite request and which register 75 in the bridge 120 to which data isto be written.

[0034] Step 510: The IDE data storage device 125 stores the data that isto be written into the indicated register 75 in the bridge into a fourthpredetermined register 85 of the IDE data storage device 125.

[0035] Step 520: The IDE data storage device 125 sets an InterruptRequest (INTRQ) signal high.

[0036] Step 530: The bridge 120 receives the INTRQ from the IDE datastorage device 125 and checks the contents of the third predeterminedregister 85.

[0037] Step 540: The implementation circuit 80 reads the contents of thepredetermined register 85 and places the read contents into the register75 of the bridge 120 indicated by the third predetermined register 85.

[0038] Step 550: The bridge 120 clears the INTRQ.

[0039] It should be obvious that no change in the hardware of the IDEdata storage device 125 is required to implement the present invention;only a change in the firmware already existing in a conventional IDEdata storage device is needed.

[0040] It should also be obvious that a second device of the presentinvention (e.g. a bridge, a host computer, or other apparatus) requirescompatible implementation circuitry to correctly respond to the controlinstructions issued by the IDE data storage device. The compatibleimplementation circuitry preferably is hardwired but may be possible toimplement in some other fashion, such as via computer code located infirmware or some other form of memory in the second device. The use ofcomputer code to respond as if it was the preferred compatibleimplementation circuitry would require the use of a microprocessor toexecute the software, increasing the cost of the second device.

[0041] Additionally, the present invention should not be limited to theuse of a bridge. For example, there is no reason that the IDE device ofthe present inverition could not be directly connected to a hostcomputer (or other apparatus) that comprises either a software form or ahardwired form of the implementation circuitry. All that is required forthe IDE data storage device of the present invention to control a seconddevice through an IDE bus connecting the IDE data storage device withthe second device is that the second device be compatible. A compatibledevice is defined as comprising the compatible implementation circuitryso that the compatible device responds to instructions issued by the IDEdata storage device as described above.

[0042] It is an advantage of the claimed invention that the IDE datastorage device can control a second device through an IDE bus, reducinghardware requirements, cost, and complexity of the second device.

[0043] Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A data storage device comprising: amicroprocessor for execution of computer code; a memory comprising thecomputer code to be executed, the computer code capable of controlling acompatible device through an Integrated Device Electronics (IDE) bus,the IDE bus connecting the data storage device with the compatibledevice; and a plurality of registers utilized by the computer code tocontrol the compatible device.
 2. The data storage device of claim 1wherein the compatible device is a bridge, the bridge connected to ahost computer system.
 3. The data storage device of claim 2 wherein thebridge communicates with the host computer system utilizing acommunication protocol incompatible with an IDE communications protocol.4. The data storage device of claim 1 wherein the compatible devicecomprises a plurality of registers and an implementation circuit, theimplementation circuit capable of decoding and acting on a first orsecond instruction issued by the data storage device when the compatibledevice receives an Interrupt Request (INTRQ) issued by the data storagedevice.
 5. The data storage device of claim 4 wherein the implementationcircuit is hardwired.
 6. The data storage device of claim 4 wherein theimplementation circuit is encoded in software or firmware.
 7. The datastorage device of claim 4 wherein when the first instruction is decodedby the implementation circuit, the implementation circuit causes a valuein a register of the compatible device indicated by a value in a firstpredetermined register of the data storage device to be transmitted tothe data storage device and clears the INTRQ signal.
 8. The data storagedevice of claim 4 wherein when the second instruction is decoded by theimplementation circuit, the implementation circuit causes a value in afourth predetermined register of the data storage device to be storedinto a register of the compatible device indicated by a value in a thirdpredetermined register of the data storage device and clears the INTRQsignal.
 9. A method for a data storage device to control a compatibledevice through a connecting Integrated Device Electronics (IDE) bus, thedata storage device comprising a microprocessor for execution ofcomputer code, a plurality of registers, and a memory comprisingcomputer code capable of controlling the compatible device, thecompatible device comprising an implementation circuit and a pluralityof registers, the method comprising: the computer code causing a firstor second instruction to be stored in a first predetermined register ofthe data storage device; the computer code causing an Interrupt Request(INTRQ) signal to be transmitted from the data storage device to thecompatible device; the compatible device receiving the INTRQ; theimplementation circuit decoding and acting on the control instruction;and the compatible device clearing the INTRQ signal.
 10. The method ofclaim 9 wherein when the implementation circuit decodes the firstinstruction, acting on the first instruction comprises: theimplementation circuit causing a value in a register of the compatibledevice indicated by a value in a first predetermined register of thedata storage device to be transmitted to the data storage device andclearing the INTRQ signal.
 11. The method of claim 9 wherein when theimplementation circuit decodes the second instruction, acting on thesecond instruction comprises: the implementation circuit causing a valuein a fourth predetermined register of the data storage device to bestored into a register of the compatible device indicated by a value ina third predetermined register of the data storage device and clearingthe INTRQ signal.
 12. The method of claim 9 wherein the compatibledevice is a bridge, the bridge connected to a host computer system. 13.The method of claim 9 wherein the implementation circuit is hardwired.14. The method of claim 9 wherein the implementation circuit is encodedin software or firmware.
 15. A bridge for use in a Host-Bridge-Devicesystem, the bridge connected to the device by an Integrated DeviceElectronics (IDE) bus, the device comprising a plurality of registers, amicroprocessor, and memory comprising computer code capable of issuing afirst or second instruction to the bridge, the bridge comprising: aplurality of resisters; and an implementation circuit capable ofdecoding and acting upon the first or second instruction issued by thedevice when the bridge receives an Interrupt Request (INTRQ) issued bythe device.
 16. The bridge of claim 15 wherein when the implementationcircuit decodes the first instruction, acting on the first instructioncomprises the implementation circuit causing a value in a register ofthe bridge indicated by a value in a first predetermined register of thedevice to be transmitted to the device and clearing the INTRQ signal.17. The bridge of claim 15 wherein when the implementation circuitdecodes the second instruction, acting on the second instructioncomprises the implementation circuit causing a value in a fourthpredetermined register of the device to be stored into a register of thebridge indicated by a value in a third predetermined register of thedevice and clearing the INTRQ signal.
 18. The bridge of claim 15 whereinthe device is a hard disk drive or an optical disc drive.
 19. The bridgeof claim 15 wherein the implementation circuit in hardwired.
 20. Adevice that controls the bridge of claim 15 by issuing the first orsecond instruction to the bridge.